### Previous GATE Questions on IC Logic Families with Solutions (1987 - Till Date)

1987

4.       Fill in the blanks of the statements below concerning the following logic families :

Standard TTL (74XXLL)

Low Power TTL (74LXX)

Low Power Schottky TTL (74LSXX)

Schottky TTL (74SXX)

Emitter Coupled Logic (ECL)

CMOS logic
a.       Among the TTL families, …………. Family requires considerably less power than the standard TTL and also has comparable propagation delay.
b.      Only the …………… family can operate over a wide range of power supply voltages.
Answer:    (a) Low Power Schottky , (b) CMOS

5.       For a logic family, given that

VOH is the minimum output high level voltage.

VOL is the maximum output low level voltage.

VIH is the minimum acceptable input low level voltage.

VIL is the maximum acceptable input low level voltage.

Then the correct relationship is
a.       VIH>VOH>VIL>VOL
b.      VOH > VIH > VIL > VOL
c.       VIH > VOH > VOL > VIL
d.      VOH > VIH > VOL > VIL

1989

1.       Among the digital IC families, ECL, TTL and CMOS :
a.       ECL has the least propagation delay
b.      TTL has the largest fan-out
c.       CMOS has the biggest noise margin
d.      TTL has the lowest power consumption

2.       A logic family has threshold voltage of 2 volts, minimum guaranteed output high voltage VOH = 4 volts, minimum accepted  input high voltage VIH = 3 volts, maximum guaranteed output low voltage VOL = 1 volt, and maximum accepted input low voltage VIL = 1.5 volts. Its noise margin is
a.       2 volts
b.      1 volts
c.       1.5 volts
d.      0.5 volts

1992

3.       The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family.

The circuit represents a
a.       NAND
b.      AND
c.       NOR
d.      OR

1994

9.       In the output stage of a standard TTL, have a diode between the emitter of the pull-up transistor and the collector of the pull-down transistor. The purpose of the diode is to isolate the output node from the power supply VCC. [TRUE / FALSE]

1995

9.       For a TTL gate, match the following

1996

1.       Schottky clamping is resorted in TTL gates
a.       To reduce propagation delay
b.      To increase noise margins
c.       To increase packing density
d.      To increase fan-out

1997

3.       In standard TTL, the ‘Totem pole’ stage refers to
a.       Multi emitter input stage
b.      Phase splitter
c.       Output buffer
d.      Open collector output stage

4.       The inverter 74ALS04 has the following specifications:
IOHmax = -0.4 mA
IOLmax = 8 mA
IIHmax = 20 µA
IILmax = -0.1 mA
The fan out based on the above will be
a.       10
b.      20
c.       60
d.      100

1998

2.       The noise margin of a TTL gate is about
a.       0.2 volts
b.      0.4 volts
c.       0.6 volts
d.      0.8 volts

14.   For the TTL circuit shown in the figure, find the current flowing through the collector of  transistor Q4, when Vo = 0.2 volts. Assume VCEsat = 0.2 volts, β = 100 and VBEsat = 0.7 volts. The α of Q1 in its inverse active mode is 0.01.

1999

2.       A Darlington emitter follower circuit is sometimes used in the output stage of a TTL gate, in order to
a.       Increase its IOL
b.      Reduce its IOH
c.       Increase its speed of operation
d.      Reduce power dissipation

3.       Commercially available ECL gates uses two ground lines and one negative power supply in order to
a.       Reduce power dissipation
b.      Increase fan-out
d.      Eliminate the effect of power line glitches or the biasing circuit

2003

3.       The output of the 74 series of TTL gates is taken from a BJT in
a.       Totem pole and Common Collector configuration
b.      Either Totem pole or Open Collector configuration
c.       Common Base configuration
d.      Common Collector configuration
9.       The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns.
 P Q R S Fanout  is minimum DTL DTL TTL CMOS Power consumption is minimum TTL CMOS ECL DTL Propagation delay is minimum CMOS ECL TTL TTL

The correct column is
a.       P
b.      Q
c.       R
d.      S

2004

5.       Figure given below shows the internal schematic of a TTL AND-OR-Invert (AOI) gate. For the inputs shown in the given figure, the output Y is

2007

4.       The circuit diagram of a standard TTL NOT gate is shown in the figure. When Vi = 2.5 volts, the modes of operation of the transistor will be
a.       Q1 reverse active, Q2 normal active, Q3 saturation and Q4 cut-off
b.      Q1 reverse active, Q2 saturation, Q3 saturation and Q4 cut-off
c.       Q1 normal active, Q2 cut-off, Q3 cut-off and Q4 saturation
d.      Q1 saturation, Q2 saturation, Q3 saturation and Q4 normal active