### GATE Previous Questions on Latches & Flip - Flops with Solutions (1987 - Till Date)

1987

1.       Choose the correct statements relating to the circuit of figure shown

Solution :

1988

1.       The circuit given below is a

a.       JK flip flop
b.      Johnson counter
c.       RS latch
d.      None of the above

1991

1.    An S-R flip flop can be converted into a T flip flop by connecting ____ to Qbar and _____ to Q.
Answer:    S to Qbar and R to Q

1992

1.       A new clocked X-Y flip flop is defined with two inputs, X and Y is in addition to the clock input. The flip flop functions as follows:

If XY = 00, the flip flop changes state with each clock pulse

If XY = 01, the flip flop state Q becomes ‘1’ with the next clock pulse

If XY = 10, the flip flop state Q becomes ‘0’ with the next clock pulse

If XY = 11, the change of state occurs with the clock pulse
a.       Write the truth table for the XY flip flop
b.      Write the excitation table for the XY flip flop
c.       It is desirable to convert a J-K flip flop into X-Y flip flop by adding some external      gates, if necessary. Draw a circuit to show how you will implement in X-Y flip flop using   a J-K flip flop.

1994

1.   For the digital circuit shown in the figure, explain what happens at nodes N1, N2, F and F’ when

1995

1.       A switch-tail ring counter is made by using a single D flip flop. The resulting circuit is a
a.       SR flip flop
b.      JK flip flop
c.       D flip flop
d.      T flip flop

2.       An SR latch is a
a.       Combinational circuit
b.      Synchronous sequential circuit
c.       One bit memory element
d.      One clock delay element

1997

1.       In a JK flip flop, we have J = Q’ and K = 1. Assume the flip flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be
a.       010000
b.      011001
c.       010010
d.      010101

1998

1.       In the figure shown is A = 1 and B = 1,  the input B is now replaced with a sequence 101010....., the output X and Y will be
a.       Fixed at 0 and 1 respectively
b.      X = 1010... while Y = 0101....
c.       X = 1010.... and Y = 1010....
d.      Fixed at 1 and 0 respectively

2000

1.       A sequential circuit using D flip flop and logic gates is shown in figure, where X and Y are the inputs and Z is output. The circuit is
a.       S-R flip flop with inputs X = R and Y = S
b.      S-R flip flop with inputs X = S and Y = R
c.       J-K flip flop with inputs X = J and Y = K
d.      J-K flip flop with inputs X = K and Y = J

2001

1.       In the figure, the output of the oscillator, V1 has 10 volts peak amplitude with zero DC value. The transfer characteristic of the Schmitt inverter is also shown in the figure. Assume that the JK flip-flop is reset at time t=0.

a.       What is the period and duty cycle of the waveform V2?
b.      What is the period and duty cycle of the waveform V3?
c.       Sketch V1, V2 and V3 for the duration 0 ≤ t ≤ 6 µsec. Clearly indicate the exact           timings when the waveforms V2 and V3 make high to low and low to high transitions.

2004

1.       A Master – Slave flip flop has the characteristic that
a.       Change in the input immediately reflected in the output.
b.      Change in the output occurs when the state of the master is affected
c.       Change in the output occurs when the state of the slave is affected
d.      Both the master and the slave states are affected at the same time.

2005

1.       The present output Qn of an edge triggered JK flip-flop is logic ‘0’. If j = 1, then Qn+1 is
a.       Cannot be determined
b.      Will be logic ‘0’
c.       Will be logic ‘1’
d.      Will race around

2007

1.       In the following circuit, binary values were applied to the inputs X and Y inputs of the NAND latch shown in the figure in the sequence indicated below:
X = 0, Y = 1;    X = 0, Y = 0;   X = 1, Y = 1;
The corresponding stable P, Q outputs will be

2008

1.       For the circuit shown in the figure, D has a transition from 0 to 1 after CLK changes from 1 to 0. Assume gate delays to be negligible.
Which of the following statements is TRUE?
a.       Q goes to 1 at the CLK transition and stays at 1
b.      Q goes to 0 at the CLK transition and stays at 0
c.       Q goes to 1 at the CLK transition and goes to 0 when D goes to 1
d.      Q goes to 0 at the CLK transition and goes to 1 when D goes to 1

2009

1.       Refer to the NAND and NOR latches shown in the figure. The inputs (P1, P2) for both the latches are first made (0, 1) and then, after a few seconds, made (1, 1). The corresponding stable outputs (Q1, Q2) are

2012

1.       Consider the given circuit. In the circuit, the race around

1. Great
Thank you

2. Complete the binary sequence at Q until 6 clock pulses with the aid of table. Assume that the
flip-flop was initially cleared and J = 1, K = Q.

CAN YOU EXPLAIN THE TRUTH TABLE

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