1987
1.
A ripple counter using negative edge
triggered D flip-flops is shown below. The flip-flops are cleared to ‘0’ at the
R input. The feedback logic is to be designed to obtain the count sequence
shown in the same figure. The correct feedback logic is :
Answer: A
1990
1.
A 4 bit modulo-16 ripple counter
uses JK flip-flops. If the propagation delay of each flip-flop is 50 nsec, the
maximum clock frequency that can be used is equal to ……
a.
20 MHz
b.
10 MHz
c.
5 MHz
d.
4 MHz
1993
1.
A pulse train with a frequency of 1
MHz is counted using a modulo 1024 ripple counter built with JK flip-flops. For
proper operation of the counter, the maximum permissible propagation delay per
flip flop stage is ____ nsec.
Answer: 50 nSec
Solution
: https://www.youtube.com/watch?v=VXYFD01hQDU
2.
A clocked sequential circuit has
three states, A, B and C and one input X. As long as the input X is ‘0’, the
circuit alternates between the states A and B. if the input X becomes
‘1’(either in state A or in state B), the circuit goes to state C and remains
in state C as long as X continues to be 1. The circuit returns to state A if
the input becomes ‘0’ once again and from then on repeats its behavior. Assume
that the state assignments are A = 00, B = 01 and C = 10.
a.
Draw the state diagram of the
circuit.
b.
Give the state table of the circuit.
c.
Draw the circuit using D flip flops.
Solution
: https://www.youtube.com/watch?v=uEwqg5Ho7Vo
1994
1.
Synchronous counters are ________
than the ripple counters.
Answer: Faster
Solution
: https://www.youtube.com/watch?v=1qBwgRPMMU8
2.
A ring oscillator consisting of 5
inverters is running at a frequency of 1 MHz. the propagation delay per each
gate is ________ nsec.
Answer: 100 nSec
Solution
: https://www.youtube.com/watch?v=aAm-0ZPJhAM
1996
1.
A state machine is required to cycle
through the following sequence of states:
ABC : 000
-> 010 ->
111 -> 100
-> 011 ->
101.
One
possible implementation of the state machine is shown in figure. Specify what
signals should be applied to each of the multiplexer inputs.
1997
1.
A sequence generator is shown in
figure. The counter status (Q0Q1Q2) is
initialized to 010 using preset/clear inputs.
The clock has a period of 50 ns and transitions take place at the rising clock
edge.
a.
Give the sequence generates a tQ0
till repeats.
b.
What is the repetition rate of the
generated sequence?
1998
1.
The figure is shows a mod – K
counter, here K is equal to
a.
1
b.
2
c.
3
d.
4
Answer: C
2.
The mod – 5 counter is shown in the
figure counts through states Q2Q1Q0 = 000,
001, 010, 011 and 100.
a.
Will the counter lockout if it
happen to be in any one of the unused states?
b.
Find the maximum rate at which the
counter will operate satisfactorily. Assume the propagation delays of flip-flop and AND gate to be tFF
and tA respectively.
1999
1.
The ripple counter shown in the
given figure is works as a
a.
Mod – 3 up counter
b.
Mod – 5 up counter
c.
Mod – 3 down counter
d.
Mod – 5 down counter
Answer: D
2.
The circuit diagram of a synchronous
counter is shown in the given figure. Determine the sequence of states of the
counter assuming that the initial state is ‘000’. Give your answer in a tabular
form showing the present state QA, QB, QC, J-K
inputs (JA, KA, JB, KB, JC,
KC) and the next state QA+, QB+, QC+.
From the table, determine the modulus of the counter.
Answer: Mod - 6
2000
1.
In the given figure, the J and K
inputs of all the four flip-flops are made high. The frequency of the signal at
output Y is
a.
0.833 KHz
b.
1.0 KHz
c.
0.91 KHz
d.
0.77 KHz
Answer: B
2001
1.
For the ring oscillator shown in teh
figure, the propagation delay of each inverter is 100 pico sec. What is the
fundamental frequency of the oscillator output?
a.
10 MHz
b.
100 MHz
c.
1 GHz
d.
2 GHz
Answer: C
2.
The digital block in the figure,
realized using two positive edge triggered D flip-flops. Assume that for t<t0,
Q1 = Q2 =0. The circuit in the digital block is given by
Answer: C
2002
1.
It is required to design a binary
mod-5 synchronous counter using AB flip-flop, such that the output Q2Q1Q0
changes as 000 -> 001 -> 010..... and so on. The truth table for the AB
flip-flop is given in figure.
a.
Write down the state table for the
mod-5 counter
b.
Obtain simplified SOP expressions
for the inputs A2, B2, A1, B1, A0
and B0 in terms of
Q2, Q1, Q0 and their complements.
c.
Hence complete the circuit diagram
for the mod-5 counter given in the figure using minimum number of 2 input NAND gate only.
2003
1.
A 0 to 6 counter consists of 3 flip
flops and a combination circuit of 2 input gate(s). The combination circuit
consists of
a.
one AND gate
b.
one OR gate
c.
one AND gate and one OR gate
d.
two AND gates
2.
A 4 bit ripple counter and a 4 bit
synchronous counter are made using flip flops having a propagation delay of 10
ns each. If the worst case delay in the ripple counter and the synchronous
counter be R and S respectively, then
a.
R = 10 ns, S = 40 ns
b.
R = 40 ns, S = 10 ns
c.
R = 10 ns, S = 30 ns
d.
R = 30 ns, S = 10 ns
Answer: B
2004
1.
In the modulo – 6 ripple counter
shown in the given figure, the output of the 2 input gate is used to clear the
JK flip flops.
The
2 input gate is
a.
NAND gate
b.
NOR gate
c.
OR gate
d.
AND gate
Answer: C
Solution : https://www.youtube.com/watch?v=2b1wBH220Oo
2005
1.
The given figure shows a ripple
counter using positive edge triggered flip-flops. If the present state of the
counter is Q2Q1Q0 = 011, then its next state Q2Q1Q0
will be
a.
010
b.
100
c.
111
d.
101
Answer: B
Solution : https://www.youtube.com/watch?v=iZWdwF2lfmw
2006
1.
Two D flip-flops are to be connected
as a synchronous counter as shown below, that goes through the following Q1Q0
sequence 00 -> 01 -> 11 ->10 -> 00
->………..
The
inputs D0 and D1 respectively should be connected as
Answer: A
2007
1.
For the circuit shown, the counter
state (Q1Q0) follows the sequence
a.
00, 01, 10, 11, 00…..
b.
00, 01, 10, 00, 01…..
c.
00, 01, 11, 00, 01…..
d.
00, 10, 11, 00, 10…..
Answer: B
2008
1.
For each of the positive edge
triggered JK flip flop used in the following figure, the propagation delay is ΔT.
Which
of the following waveforms correctly represents the output at Q1?
Answer: B
Solution
: https://www.youtube.com/watch?v=N7ZYplccPcA
2009
1.
What are the counting stages (Q1,
Q2) for the counter shown in the figure below?
a.
11, 10, 00, 11, 10….
b.
01, 10, 11, 00, 01….
c.
00, 11, 01, 10, 00…..
d.
01, 10, 00, 01, 10…..
Answer: A
Solution : https://www.youtube.com/watch?v=marTcMTzg0Y
2010
1.
Assuming that all flip-flops are in
reset condition initially, the count sequence observed at QA in the
circuit shown is
a.
0010111….
b.
0001011….
c.
0101111….
d.
0110100….
Answer: D
Solution : https://www.youtube.com/watch?v=UsicxIAMqx0
2011
1.
When the output Y in the circuit below
is ‘1’, it implies that data has
a.
Changed from ‘0’ to ‘1’
b.
Changed from ‘1’ to ‘0’
c.
Changed in either direction
d.
Not changed
Answer: A
2.
The output of a 3 stage Johnson
(twisted ring) counter is fed to a digital to analog (D/A) converter as shown
in the figure below. Assume all states of the counter to be unset initially.
The waveform which represents the D/A converter output Vo is
Answer: A
Solution : https://www.youtube.com/watch?v=g9vVeVizDIM
3.
Two D flip-flops are connected as a
synchronous counter that goes through the following QB QA
sequence 00 -> 11 -> 01 -> 10
-> 00-> ………. The connections of the inputs DA and DB
are
Answer: D
2012
1.
The state transition diagram for the
logic circuit shown is
Answer: D
Solution : https://www.youtube.com/watch?v=S2ytlAcBkFk
2014
1.
Five JK flip flops are cascaded to
form the circuit shown in figure. Clock pulses at a frequency of 1 MHz are
applied as shown. The frequency (in KHz) of the waveform at Q3 is …………
Answer: 62.5
Solution : https://www.youtube.com/watch?v=ID70DQCpDCg
2.
The digital logic shown in the
figure satisfies the given state diagram when Q1 is connected to input A of the
XOR gate. Suppose the XOR gate is replaced by the XNOR gate. Which one of the
following options preserves the state diagram?
Answer: D
Solution : https://www.youtube.com/watch?v=tBqtKpt1oSE
3.
In the circuit shown, choose the
correct timing diagram of the output (y) from the given waveforms W1, W2, W3 and
W4.
a.
W1
b.
W2
c.
W3
d.
W4
Answer: C
4.
The outputs of the two flip-flops
Q1, Q2 in the figure shown are initialized to 0, 0. The sequence generated at
Q1 upon application of clock signal is
a.
01110….
b.
01010…..
c.
00110….
d.
01100…..
Answer: D
Solution : https://www.youtube.com/watch?v=wNoctGWwcfs
5.
The circuit shown in the figure is a
a.
Toggle flip flop
b.
JK flip flop
c.
SR Latch
d.
Master – Slave D flip flop
Answer: D
Solution : https://www.youtube.com/watch?v=AvKzOVpre_k
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