### GATE Practice Problems on JFET (Junction Field Effect Transistor)

1.       An N-channel JFET has VP = -4 volts and IDSS = 10 mA.
a.       Find the minimum VDS for the device to operate in pinch-off, when VGS = -2 volts.
b.      Find the drain current for VGS = -2 volts, when VDS is 3 volts and 5 volts.

2.       The JFET in the circuit has VP = - 3 volts, IDSS = 9 mA. Find the values of all resistors so that VG = 5 volts, ID = 4 mA and VD = 11 volts. Design for 0.05 mA in the voltage divider.

3.       An N-channel silicon JFET has a donor concentration of 2 x 1021 /m3 and a channel width of 4 µm.
a.       Find the pinch off voltage, VP
b.      Find the saturation voltage, VDSsat, if VGS is  – 2 volts.

4.       The Q-point of a JFET in a source self-bias arrangement is chosen at VGS = - 1.5 volts and ID = 5 mA. Find the value of the resistance RS.

5.       An N-channel JFET has IDSS = 12 mA and the Transconductance of 4mA/V when VGS = 0 volts.
a.       Find the pinch off voltage, VP
b.      Find the drain current when VGS = - 2 volts.

6.       An N-channel JFET has pinch off voltage of – 4.5 volts and IDSS = 9 mA.
a.       At what value of VGS in the pinch off region will ID equal to 3 mA?
b.      What is the value of VDS(sat), when ID = 3 mA?

7.       For the given JFET, IDSS = 10 mA and VP = - 4 volts. Find the quiescent values of ID and VDS, when VGS = - 1.5 volts. Assume that JFET is biased in pinch off region.

8.       For the circuit shown, find the Q-point, when VGS = - 3 volts.

9.       For the P-channel JFET shown, find the Q-point if IDSS = 18 mA and VP = 5 volts.

10.   An N-channel JFET has IDSS = 16 mA and VP = - 6 volts. Calculate the drain current and VDS(sat) when VGS = - 4 volts.

11.   A P-channel JFET has a pinch off voltage of 8 volts. At what value of VGS does VDS(sat) = - 3 volts?

12.   An N-channel JFET has pinch off voltage of – 5.8 volts and IDSS = 15 mA. Find the value of ID when VGS is 0 volts, - 2 volts and – 6.5 volts.

13.   An N-channel JFET having a pinch off voltage of – 3.5 volts has a saturation current of 2.3 mA when VGS = - 1 volt. What is its saturation current when VGS = 0 volts and -2 volts.

14.   A P-channel JFET has a pinch off voltage of 6 volts and IDSS = 18 mA. At what value of VGS in the pinch off region will ID equal 6 mA? What is the value of VDS at pinch off point?

15.   The JFET shown has IDSS = 14 mA and VP = - 5 volts. Determine the Q-point for
a.       VGS = - 3.6 volts
b.      VGS = - 3 volts
c.       VGS = - 1.7 volts

16.   Find the Q-point of the JFET shown, if IDSS = 6 mA and VP = - 3 volts.

17.   Determine the values of ID,VGS and VDS for the JFET shown, if IDSS = 25 mA and VP = 8 volts.

18.   Determine the values of ID, VGS and VDS of the JFET circuit shown, if IDSS = 2.42 mA and VP = - 4 volts.

19.   Find the values of ID and VDS of the N-channel JFET shown, if IDSS = 12 mA and VP = - 5 volts.

### GATE Questions on MOSFET, CMOS & Introduction to VLSI (1987 to Till Date)

1988

1.       In MOSFET devices, the N-channel type is better than the P-channel type in the following respects
a.       It has better noise immunity
b.      It is faster
c.       It is TTL compatible
d.      It has better drive capability

1989
1.       In a MOSFET, the polarity of the inversion layer is the same as that of the
a.       Charge on the gate electrode
b.      Minority carriers in the drain
c.       Majority carriers in the substrate
d.      Majority carriers in the source

1990
1.      Which of the following effects can be caused by a rise in the temperature ?
a. Increase in MOSFET current
b. Increase in BJT current
c. Decrease in MOSFET current
d. Decrease in BJT current

1991

1.       In the figure shown, the n-channel MOSFETs are identical and their current voltage characteristics are    given by the following expressions.
Find the current IDC as shown

1992
1.   An n-channel MOSFET having a threshold voltage of 2 volts is used in the circuit shown in figure. Initially the transistor is OFF and is in steady state. At time t = 0, a step voltage of magnitude of 4 volts is applied to the input so that the MOSFET turns ON instantaneously.
Draw the equivalent circuit and calculate the time taken to the output Vo to fall to 5 volts.
The device constant of the MOSFET, K = 5 mA/ V2, CDS =0 and CDG = 0.

1994
1.       The threshold voltage of an n-channel MOSFET  can be increased by
a.       Increasing the channel dopant concentration
b.      Reducing the channel dopant concentration
c.       Reducing the gate oxide thickness
d.      Reducing the channel length

2.       The transit time of the current carriers through the channel of an FET decides its ……………. characteristics.

3.       Channel current is reduced on application of a more positive voltage to the gate of a depletion mode n-channel MOSFET.  (TRUE / FALSE)

4.       A typical CMOS inverter has the voltage transfer characteristic (VTC) curve as shown in the figure.               Evaluate the value of the inverter threshold VINV, which is the value of the input at which Vo falls by                           ΔVo = VTn + VTp.

1995

1.   Calculate the capacitance of a circular MOS capacitor, of 0.5 mm dia and having a SiO2 layer of 80 mm thickness, under strong accumulation. Assume the relative dielectric constant of SiO2, Ԑr = 4 and Ԑo = 8.854 X 10-14 F/cm. calculate the breakdown voltage of the capacitor if the dielectric strength of SiO2 film is 107 V/cm.

1996

1.       The n-channel MOSFET shown in figure is used as a voltage variable resistor. Determine the expression for the resistance and compute its value for Vi. Neglect body effect.
MOSFET Data :
Threshold voltage, VT = 1 volt
Channel Length Modulation parameter, λ = - 0.3 V-1
Transconductance parameter, KN(W/L) = 40 µA/V2

Answer:    25 kΩ (without CLM), 7.5 kΩ (with CLM)

2.       A Silicon N-channel MOSFET has a threshold voltage of 1 volts and oxide thickness of  400 Ao.  [Ɛr (SiO2) = 3.9, Ɛo = 8.854 x 10-14 F/cm, q = 1.6 x 10-19]. The region under the gate is ion implanted for threshold voltage tailoring. The doping and type of the implant (assumed to be a sheet charge at the interface) required to shift the threshold voltage to -1 volt are…

a.       1.08 x 1012/cm3,   P –type
b.      1.08 x 1012/cm3,   N -type
c.       5.4 x 1011/cm3,   P -type
d.      5.4 x 1011/cm3,   N -type

Solution :

3.       An N-channel silicon (EG = 1.1 eV) MOSFET was fabricated using N+ poly silicon gate and the threshold voltage was found to be 1 volt. Now if the gate is changed to P+ poly silicon, other things remaining the same, the new threshold voltage should be………..volts.
a.       -0.1
b.      0
c.       1.0
d.      2.1

1997
1.       For a MOS capacitor fabricated on a P-type semiconductor, strong inversion occurs when
a.       Surface potential is equal to Fermi level
b.      Surface potential is zero
c.       Surface potential is negative is negative and equal to Fermi potential in magnitude
d.      Surface potential is positive and equal to twice the Fermi potential

2.       The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because
a.       The driver transistor has larger threshold voltage than the load transistor
b.      The driver transistor has larger leakage currents compared to the load transistor
c.       The load transistor has a smaller W/L ratio compared to the driver transistor
d.      None of the above

3.       Given NMOS circuit as shown. The specifications of the circuit are :
VDD = 10 volts, β = µnCox(W/L) = 10-4 Amp/V2, VT = 1 volt and IDS = 0.5 mA.
Evaluate VDS and RD. Neglect body effect.

1998

1.       The threshold voltage for each transistor in figure is 2 volts. For this circuit to work as an inverter, Vi must take the values

a.       -5 volts and 0 volts
b.      -5 volts and 5 volts
c.       0 volts and 3 volts
d.      3 volts and 5 volts

1999

1.       In the CMOS inverter circuit shown in figure, the input Vi makes a transition from VOL (= 0 volts) to VOH (= 5 volts). Determine the High to Low propagation delay time (tpHL) when it is driving a capacitive load (CL) of 20 pF.
Device data :

2001

1.       MOSFET can be used as a
a.       Current controlled capacitor
b.      Voltage controlled capacitor
c.       Current controlled inductor
d.      Voltage controlled inductor

2.       The effective channel length of a MOSFET in saturation decreases with increase in
a.       Gate voltage
b.      Drain voltage
c.       Source voltage
d.      Body voltage

2002

1.       Consider the following statements in connection with the CMOS inverter in figure, where both the MOSFETs are of enhancement type and both have a threshold voltage of 2 volts.
S1: T1 conducts when VI 2 volts.
S2: T1 is always in saturation when Vo = 0 volts.
Which  of the following is correct.

a.       Only S1 is TRUE
b.      Only S2 is TRUE
c.       Both are TRUE
d.      Both are FALSE

2003

1.       For an N channel type MOSFET, if the source is connected at a higher potential than that of the bulk (i.e. VSB > 0 volts), the threshold voltage VT of the MOSFET will
a.       Remain unchanged
b.      Decrease
c.       Change polarity
d.      Increase

2.   When the gate to source voltage (VGS) of a MOSFET with threshold voltage of 400 mV. The drain current observed is 1 mA. Neglecting the channel length modulation effect, and assuming that the MOSFET is operating at saturation, the drain current for an applied VGS of 1400 mV is
a.       0.5 mA
b.      2.0 mA
c.       3.5 mA
d.      4.0 mA

3.   If P is passivation, Q is n-well implant, R is metallization and S is source/drain diffusion, then the order in which they are carried out in a standard n-well CMOS fabrication process is
a.       P-Q-R-S
b.      Q-S-R-P
c.       R-P-S-Q
d.      S-R-Q-P

2004

1.       The given figure is the voltage transfer characteristic of

2.       Consider the following statements S1 and S2.
S1: the threshold voltage (VT) of a MOS capacitor decreases with increase in gate oxide thickness
S2: the threshold voltage (VT) of a MOS capacitor decreases with increase in substrate doping concentration.
Which of the following is correct?

a.       S1 is FALSE and S2 is TRUE
b.      Both S1 and S2 are TRUE
c.       S1 is TRUE and S2 is FALSE
d.      Both S1 and S2 are FALSE

3.   The drain of an N channel MOSFET is shorted to the gate so that VGS = VDS. The threshold voltage (VT) of MOSFET is 1 volt. If the drain current (ID) is 1 mA for VGS = 2 volts, then for VGS = 3 volts, ID is
a.       2 mA
b.      3 mA
c.       9 mA
d.      4 mA

2005

1.       An N-channel MOSFET and its transfer curve is shown in figure, then the threshold voltage is

2.       Both transistors T1 and T2 in figure have a threshold voltage of 1 volt. The device parameters K1 and K2 of T1 and T2 are 36 µA/v2 and 9 µA/v2 respectively. The output voltage Vo is

3.   A MOS capacitor made using P type substrate is in the accumulation mode. The dominant charge is due to the presence of
a.       Holes
b.      Electrons
c.       Positively charged ions
d.      Negatively charged ions

2006

1.       An N-channel depletion MOSFET has the following two points on its ID verses VGS curve are
(i)    VGS = 0 at ID = 12 mA and
(ii)   VGS = -6 volts  at  ID = 0 mA
Which of the following Q-points will give the highest Transconductance gain for small signals?
a.       VGS = -6 volts
b.      VGS = -3 volts
c.       VGS =  0 volts
d.      VGS =  3 volts

2007

1.       Group I lists four different semiconductor devices. Match each device in Group I with its characteristic property in Group II.

2.       In the CMOS inverter circuit shown, if the Transconductance parameters of the NMOS and PMOS transistors are Kn = Kp = µnCox(Wn/Ln) = µpCox(Wp/Lp) = 40 µA/V2 and their threshold voltages are VTn = |VTp| = 1 volt, the current I is

a.       0 Amp
b.      25 µA
c.       45 µA
d.      90 µA

3.   The figure shows the high frequency capacitance – voltage (C – V) characteristics of MOS capacitor having an area of 1x10-4 cm2. Assume that the permittivity of silicon and SiO2 are 1x10-12 and 3.5x10-13 F/cm respectively.

i.                     The gate oxide thickness in the MOS capacitor is
a.       50 nm
b.      143 nm
c.       350 nm
d.      1 µm
ii.                   The maximum depletion layer width in silicon is
a.       0.143 µm
b.      0.857 µm
c.       1 µm
d.      1.143 µm
iii.                  Consider the following statements about the C – V characteristics plot :
S1:  The MOS capacitor has an N type substrate
S2:  If the positive charges are introduced in the oxide, the C – V plot will shift to the left.
Then which one of the following is TRUE .
a.       Both S1 and S2 are TRUE
b.      S1 is TRUE and S2 is FALSE
c.       S1 is FALSE and S2 is TRUE
d.      Both S1 and S2 are FASLE

2008

1.       A silicon wafer has 100nm of oxide on it and is inserted in a furnace at a temperature above 1000oC for further oxidation in dry oxygen. The oxidation rate
a.       Is independent of current oxide thickness and temperature
b.      Is independent of current oxide thickness but depends on temperature
c.      Slows down as the oxide grows
d.      Is zero as the existing oxide prevents further oxidation

2.       The drain current of a MOSFET in saturation is given by ID = K(VGS-VT)2, where K is a constant. The magnitude of the Transconductance gm is

3.       For the circuit shown in the following figure, transistors M1 and M2 are identical NMOS transistors. Assume that M2 is in saturation and the output is unloaded. The IX is related to Ibias as

4.       The measured Transconductance gm of an NMOS transistor operating in the linear region is plotted against the gate voltage VG at constant drain voltage VD. Which of the following figures represents the expected dependence of gm on VG?

5.    Two identical NMOS transistors M1 and M2 are connected as shown below. Vbias is chosen so that both transistors are in saturation. The equivalent gm of the pair is defined to be dIout / dVi at constant Vout, is

a.       The sum of individual gm’s of the transistors
b.      The product of individual gm’s of the transistors
c.       Nearly equal to the gm of M1
d.      Nearly equal to gm1/gm2 of M2

2009

1.       The full forms of the abbreviations TTL and CMOS in reference to logic families are
a. Triple Transistor Logic and Chip Metal Oxide semiconductor
b. Tristate Transistor Logic and Chip Metal Oxide semiconductor
c.  Transistor Transistor Logic and Complementary Metal Oxide semiconductor
d. Tristate Transistor Logic and Complementary Metal Oxide semiconductor

2.       Consider the following two statements about the internal conditions in an N channel MOSFET operating in the active region.
S1: the inversion charge decreases from source to drain
S2: the channel potential increases from source to drain
Which of the following is correct?
a.       Both are TRUE
b.      Both are FALSE
c.       Both are TRUE, but S2 is not a reason for S1
d.      Both are TRUE, and S2 is a reason for S1.

Consider the CMOS circuit shown, where the gate voltage VG of the N channel MOSFET is increased from zero, while the gate voltage of the P channel MOSFET is kept constant at 3 volts. Assume that, for both transistors, the magnitude of the threshold voltage is 1 volts and the product of the transconductance parameter and the (W/L) ratio i.e. the quantity µcox(W/L) is 1 mA/V2

i.                     For small increase in VG beyond 1 volt, which of the following gives the correct description of the region of operation of each MOSFET?
a.       Both are in saturation region
b.      Both are in triode region
c.       NMOS is in triode region and PMOS is in saturation region
d.      NMOS is in saturation region and PMOS is in triode region
ii.                   Estimate the output voltage, Vo for VG = 1.5 volts. (Hint: use the appropriate current voltage equation for each MOSFET, based on the answer to above question)

2010

1.       At room temperature, a possible value for the mobility of electrons in the inversion layer of a silicon N channel MOSFET is (in cm2/volt-sec)
a.       450
b.      1350
c.       1800
d.      3600

2.       The gate oxide in a CMOS process is preferably grown using
a.       Wet oxidation
b.      Dry oxidation
c.       Epitaxial deposition
d.      Ion implantation

2011

1.       In the circuit shown below, for the MOS transistors, µncox = 100 µA/V2 and the threshold voltage VT = 1 volt. The voltage VX at the source of the upper transistor is

a.       1 volt
b.      2 volts
c.       3 volts
d.      0.367 volts

2012

1.       In the circuit shown below, the output expression ‘Y’ is

2.       In the CMOS circuit shown, electron and hole motilities are equal, and M1 and M2 transistors are equally sized. The device M1 is in the linear region if

3.       In the three dimensional view of a silicon N channel MOS transistor shown below, δ = 20 nm. The transistor is of width 1 µm. The depletion width formed at every PN junction is 10 nm. The relative permittivity’s of Si and SiO2 are 11.7 and 3.9 respectively and Ɛ0 = 8.9 X 10-12 F/m.

i.        The gate – source overlap capacitance is approximately
a.       0.7 fF
b.      0.7 pF
c.       0.35 fF
d.      0.24 fF
ii.      The source – body capacitance approximately
a.       2 fF
b.      7 fF
c.       2 pF
d.      7 pF

2013

1.       In IC technology, Dry oxidation(using dry oxygen) as compared to Wet oxidation (using stream or water vapor) produces………..
a.       Superior quality oxide with a higher growth rate
b.      Inferior quality oxide with a higher growth rate
c.       Inferior quality oxide with a lower growth rate
d.      Superior quality oxide with a lower growth rate
2.       In MOSFET operating in saturation region, the channel length modulation effect causes
a.       An increase in gate source capacitance
b.      A decrease in Transconductance
c.       A decrease in unity gain bandwidth product
d.      A decrease in output resistance
2014
Set – 1 (15th February 2014 (Forenoon))

1.       If the fixed positive charges are present in the gate oxide of an N channel enhancement type MOSFET, it will lead to
a.       a decrease in the threshold voltage
b.      channel length modulation
c.       an increase in substrate leakage current
d.      an increase in accumulation capacitance

2.       A depletion type N channel MOSFET is biased in its linear region for use as a voltage controlled resistor.    Assume threshold voltage VTH = -0.5 volts, VGS = 2.0 volts, VDS = 5 volts, W/L = 100, Cox = 10-8 F/cm2 and µn = 800 cm2/volt-sec. The value of the voltage controlled resistor (in ) is …..

SET – 2 (15th February 2014 (Afternoon))

1.       In CMOS technology, shallow P – well or N – well regions can be formed using
a.       low pressure chemical vapor deposition
b.      low energy sputtering
c.       low temperature dry  oxidation
d.      low energy ion – implantation

2.       For the N channel MOS transistor shown in the figure, the threshold voltage VTH is 0.8 volts. Neglect channel length modulation effects. When the drain voltage VD = 1.6 volts, the drain current ID was found to be 0.5 mA. If VD is adjusted to be 2 volts by changing the values of R and VDD, the new value of ID (in mA) is

a.       0.625
b.      0.75
c.       1.125
d.      1.5

3.       For the MOSFETs shown in the figure, the threshold voltage |Vt| = 2 volts and K = 0.5µcox(W/L) = 0.1 mA/V2. The value of ID (in mA) is …………

SET – 3  (16th February 2014 (Forenoon))

1.       In MOSFET fabrication, the channel length is defined during the process of
a.       Isolation oxide growth
b.      Channel stop implantation
c.       Poly-silicon gate patterning

2.       The slope of the ID vs. VGS curve of an N channel MOSFET in linear region is 10-3 -1 at VDS = 0.1 volts. For the same device, neglecting channel length modulation, the slope of the ID vs. VGS curve (in A/V) under saturation regime is approximately…………….

3.       An ideal MOS capacitor has boron doping concentration of 1015 cm-3 in the substrate. When a gate voltage is applied, a depletion region of width 0.5 µm is formed with a surface (channel) potential of 0.2 volts. Given that Ԑo = 8.854 x 10-14 F/cm and the relative permittivity’s of silicon and silicon dioxide are 12 and 4 respectively. The peak electric field (in V/µm) in the oxide region is ……………..

4.       For the MOSFET M1 shown in the figure, assume W/L = 2, VDD = 2.0 volts, µncox = 100 µA/V2 and VTH = 0.5 volts. The transistor M1 switches from saturation region  to linear region when Vin (in volts) is …………..

2015

1.       Which one of the following processes is preferred to form the gate dielectric (SiO2) of MOSFET?
a.       Sputtering
b.      Molecular Beam Epitaxy
c.       Wet Oxidation
d.      Dry Oxidation

2.       In the circuit shown, the both the enhancement mode NMOS transistors have the following characteristics: Kn = µn.Cox(W/L) = 1 mA/V2, VTN = 1 volt.
Assume that the channel length modulation parameter λ is zero and body is shorted to source. The minimum supply voltage VDD (in volts) needed to ensure that transistor M1 operates in saturation mode of operation is ___________________

3.       The current in an enhancement mode NMOS transistor biased in saturation mode was measured to be 1 mA at a drain to source voltage of 5 volts. When the drain – source voltage was increased to 6 volts, while keeping gate-source voltage same, the drain current increased to 1.02 mA. Assume that drain to source saturation voltages is much smaller than the applied drain source voltage. The channel length modulation parameter λ (in V-1) is __________

4.   For the NMOSFET in the circuit shown, the threshold voltage is Vth greater than zero. The source voltage VSS is varied from 0 to VDD. Neglecting the channel length modulation, the drain current ID as a function of VSS is represented by

5.   A MOSFET in saturation has a drain current of 1 mA for VDS = 0.5 volts. If the channel length modulation coefficient is 0.05 V-1, the output resistance (in kΩ) of the MOSFET is ________

6.   In MOS capacitor with an oxide layer thickness of 10 nm. The maximum depletion layer thickness is 100 nm. The permittivity’s of the semiconductor and the oxide layer are εs and εox  respectively. Assuming εsox = 3, the ratio of the maximum capacitance to the minimum capacitance of this MOS capacitor is ____________