GATE 1999 ECE Video Solution on Digital Circuits (Digital Electronics)

1. The logical expression Y = A + A’B is equivalent to
a. AB
b. A’B
c. A’ + B
d. A + B
Solution :

2. A Darlington emitter follower circuit is sometimes used in the output stage of a TTL gate, in order to
a. Increase its IOL
b. Reduce its IOH
c. Increase its speed of operation
d. Reduce power dissipation
Solution :

3. Commercially available ECL gates uses two ground lines and one negative power supply in order to
a. Reduce power dissipation
b. Increase fan-out
c. Reduce loading effect
d. Eliminate the effect of power line glitches or the biasing circuit
Solution :

4. The resolution of a 4 bit counting ADC is 0.5 volts. For an analog input of 6.6 volts, the digital output of the ADC will be
a. 1011
b. 1101
c. 1100
d. 1110
Solution :

5. The minimized form of the logical expression

Solution :

6. For a binary half – subtractor having two inputs A and B, the correct set of logical expressions for the outputs D (= A minus B) and X (= borrow) are

Solution :

7. The ripple counter shown in the given figure is works as a

a. Mod – 3 up counter
b. Mod – 5 up counter
c. Mod – 3 down counter
d. Mod – 5 down counter
Solution :

8. If CS = A15’A14A13 is used as the chip select logic of a 4K RAM in an 8085 system, then its memory range will be
a. 3000 – 3FFFFH
b. 7000 – 7FFFH
c. 5000 – 5FFFH and 6000 – 6FFFH
d. 6000 – 6FFFH and 7000 – 7FFFH
Solution :

9. The circuit diagram of a synchronous counter is shown in the given figure. Determine the sequence of states of the counter assuming that the initial state is ‘000’. Give your answer in a tabular form showing the present state QA, QB, QC, J-K inputs (JA, KA, JB, KB, JC, KC) and the next state QA+, QB+, QC+. From the table, determine the modulus of the counter.

Answer: Mod - 6
Solution :

10. In a certain application, four inputs A, B, C, D (both true and complement forms available) are fed to logic circuit, producing an output F which operates a relay. The relay turns on when F(ABCD) = 1 for the following states of the inputs (ABCD): ‘0000’, ‘0010’, ‘0101’, ‘0110’, ‘1101’ and ‘1110’. States ‘1000’ and ‘1001’ do not occur, and for the remaining states, the relay is off. Minimize F with the help of a Karnaugh map and realize it using a minimum number of 3 input NAND gates.

Solution :

11. An 8085 assembly language program is given below.

Solution :

1 comment:

  1. Where is the solution of last question..????


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