### Concepts of Digital Logic Gates - Useful GATE and UPSC IES ESE exams

Digital  Logic gates

Definition:  A Logic Gate can have one or more inputs but it should have only one output.

Types of Logic Gates: AND, OR, NOT, Buffer, XOR, XNOR, NAND and NOR.

The following digram shows all types of logic gates available with their truth tables.

• Output of AND gate is '1' when all of its inputs are at '1'.
• Output of OR gate is '0' when all of its inputs are at '0'.
• Output of Buffer is same as input. The advantage is output has higher drive strenth compared to input, so it can drive more inputs(i.e. more inputs can be driven by the output without loss of signal strength).
• Output of Inverter is compliment of input. Here also output has more drive strength than input.
• Output of NAND gate is '0' when all of its inputs are at '1'. (or) Output of NAND gate is '1' when at least one of the input is '0'.
• Output of OR gate is '1' when all of its inputs are at '0'. (or) Output of NOR gate is '0' when at least one of the input is '1'.
• Output of XOR gate is '1' when odd number of inputs are at '1'. In case of two input XOR gate, Output is '1' when one of the input is '1' and other is at '0'. In other words, when inputs are dissimilar, output of two input XOR gate is '1'.
• Output of XNOR gate is '1' when even number of inputs are at '1' or when all the inputs are at '1'. In case of two input XNOR gate, Output is '1' when both inputs are at either '0' or '1'. In other words, Output of XNOR gate is '1' when both inputs are same.

Two input XNOR gate is also called as "Coincidence Gate", as when both inputs coincides, output is '1'.

XOR and XNOR gates are mainly used in Parity Generation and Parity Detection circuits.

Q:  why NAND and NOR gate are called "Universal Gates" ?

Ans: NAND and NOR gate are called "Universal Gates", because by using either only NAND gates or NOR gates, any combinational logic function (Boolean Function) can be realized. The following diagram shows how can all gates can be realized using only NAND gates as well as NOR gates.

Note: A two input XOR gate can be realized using four two input NAND gates or five two input NOR gates.

A two input XNOR gate can be realized using four two input NOR gates or five two input NAND gates.

Q: why "AND, OR and INVERER " gates are called "complete set of gates"?

Ans: Using AND gates, OR gates and INVERTERs , any combinational logic function can be realized.

Q: How can a two input XOR gate acts as INVERTER or BUFFER?

Ans: For a two input XOR gate, if one of the input is at '1' then output is always equal to complement of other input. Hence a two input XOR gate acts as INVERTER.

For a two input XOR gate, if one of the input is at '0' then output is always equal to same as other input. Hence a two input XOR gate acts as BUFFER. Look at the following diagram for understanding.

Q: How can a two input XNOR gate acts as INVERTER or BUFFER?

Ans: For a two input XNOR gate, if one of the input is at '0' then output is always equal to complement of other input. Hence a two input XNOR gate acts as INVERTER.

For a two input XNOR gate, if one of the input is at '1' then output is always equal to same as other input. Hence a two input XNOR gate acts as BUFFER. Look at the following diagram for understanding.

Q: How can  N input NAND gate acts as INVERTER?

Ans: when all the inputs of NAND gate are tied together, then output of NAND gate is complement of input. So it can acts as Inverter.

Q: How can a 2 input NAND gate acts as Swtich? (or) How to enable or disable the input of NAND gate to reach output?

Ans: Enable Operation: when one terminal of two input NAND gate is at '1', then output is complement of input connected at other terminal. So input is allowed to reach output but in complemented form.

Disable Operation: when one terminal of two input NAND gate is at '0', then output is ONE irrespective of input connected at other terminal. So input is not allowed to reach output.

Q: How can  N input NOR gate acts as INVERTER?

Ans: when all the inputs of NOR gate are tied together, then output of NOR gate is complement of input. So it can acts as Inverter.

Q: How can a 2 input NOR gate acts as Swtich? (or) How to enable or disable the input of NOR gate to reach output?

Ans: Enable Operation: when one terminal of two input NOR gate is at '0', then output is complement of input connected at other terminal. So input is allowed to reach output but in complemented form.

Disable Operation: when one terminal of two input NAND gate is at '1', then output is ONE irrespective of input connected at other terminal. So input is not allowed to reach output.

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