Wednesday, June 25, 2014

GATE 2013 ECE Video Solutions on Analog Circuits (Analog Electronics)

1. In the circuit shown below, what is the output voltage (Vout), if a silicon transistor Q and an ideal OP-AMP are used?

a. - 15 volts
b. - 0.7 volts
c. + 0.7 volts
d. + 15 volts
Answer: B

2. In a voltage – voltage feedback as shown below, which one of the following statements is TRUE, if the gain K is increased?

a. The input impedance increases and output impedance decreases
b. The input impedance increases and output impedance increases
c. The input impedance decreases and output impedance decreases
d. The input impedance decreases and output impedance increases

3. The small signal resistance (ie. dVB/dID) in KΩ offered by the n – channel MOSFET M shown in the figure below, at a bias point of VB = 2 volts is (device data for M: device Transconductance parameter KN = µNCOX(W/L) = 40 µA/V2, threshold voltage VTN = 1 volt, and neglecting body effect and channel length modulation effects)

a. 12.5
b. 25
c. 50
d. 100

4. The ac schematic of an NMOS common source stage is shown in the figure below, where part of the biasing circuit has been omitted for simplicity. For the n – channel MOSFET M, the Transconductance gm = 1 mA/V and body effect and channel length modulation effect are to be neglected. The lower cutoff frequency in Hz of the circuit approximately at

a. 8
b. 32
c. 50
d. 200

5. In the circuit shown below, the OP-AMPs are ideal. Then Vout in volts is

a. 4
b. 6
c. 8
d. 10

6. A voltage 1000sinωt volts is applied across YZ. Assuming ideal diodes, the voltage measured across WX in volts is

a. Sinωt
b. (Sinωt + |Sinωt|) / 2
c. (Sinωt - |Sinωt|) / 2
d. 0 for all t

7. In the circuit shown below, the knee current of ideal zener diode is 10 mA. To maintain 5 volts across the load RL, the minimum value of RL in Ω’s and the minimum power rating of the zener diode in mW respectively are

a. 125 and 125
b. 125 and 250
c. 250 and 125
d. 250 and 250

8. In the circuit shown below, the silicon NPN transistor Q has a very high value of β. The required value of R2 in KΩ to produce IC = 1 mA is

a. 20
b. 30
c. 40
d. 50

Monday, June 23, 2014

GATE 1991 ECE Video Solutions on Digital Circuits (Digital Electronics)

1. Two dimensional addressing of 256 X 8 bit ROM using 8 to 1 selectors requires _______ (how many?) NAND gates.

2. The CMOS equivalent of the following nMOS gate (shown in figure) is ________ (Draw the circuit).

Answer:(A + BC)'

3. A bit stored in a FAMOS device can be erased by ___________.
Answer:UV Light

4. In the figure, the Boolean expression for the output in terms of inputs A, B and C when the clock CK is high, is given by ____________

Answer:(A + B)C

5. The program given below is run on an 8085 based microcomputer system. Determine the contents of the registers: PC, SP, B, C, H, L after a halt instruction is executed.


6. The four variable function f is given in terms of min-terms as f(A, B, C, D) = ∑m(2,3,8,10,11,12,14,15). Using the K-map minimize the function in the sum of products form. Also, give the realization using only two input NAND gates.
Answer: f = AD' + AC + B'C and No.of NAND gates required = 6

7. An S-R flip flop can be converted into a T flip flop by connecting ____ to Qbar and _____ to Q.
Answer: S to Qbar and R to Q

GATE 1992 ECE Video Solutions on Digital Circuits (Digital Electronics)

1. The logic realized by the circuit shown in figure is


2. Choose the correct statement(s) from the following:
a. PROM contains a programmable AND array and a fixed OR array
b. PLA contains a fixed AND array and a programmable OR array
c. PROM contains a fixed AND array and a programmable OR array
d. PLA contains a programmable AND array and a programmable OR array
Answer: C & D

3. The figure shows the circuit of a gate in the Resistor Transistor Logic (RTL) family.

The circuit represents a
b. AND
c. NOR
d. OR

4. The initial contents of the 4 bit serial in serial out, right shift, shift register shown in figure, are 0110. After three clock pulses are applied, the contents of the shift register will be

a. 0000
b. 0101
c. 1010
d. 1111

5. In an 8085 microprocessor system with memory mapped I/O,
a. I/O devices have 16 bit addresses
b. I/O devices are accessed using IN and OUT instructions
c. There can be a maximum of 256 input devices and 256 output devices
d. Arithmetic and logic operations can be directly performed with the I/O data.

6. The following program is run on 8085 microprocessor:

At the completion of the execution of the program, the program counter of the 8085 contains _____________ and the stack pointer contains _______________.

7. A new clocked X-Y flip flop is defined with two inputs, X and Y is in addition to the clock input. The flip flop functions as follows:
If XY = 00, the flip flop changes state with each clock pulse
If XY = 01, the flip flop state Q becomes ‘1’ with the next clock pulse
If XY = 10, the flip flop state Q becomes ‘0’ with the next clock pulse
If XY = 11, the change of state occurs with the clock pulse
a. Write the truth table for the XY flip flop
b. Write the excitation table for the XY flip flop
c. It is desirable to convert a J-K flip flop into X-Y flip flop by adding some external gates, if necessary. Draw a circuit to show how you will implement in X-Y flip flop using a J-K flip flop.


8. Dual slope integration type analog to digital converter provide
a. Higher speeds compared to all other types of A/D converters
b. Very good accuracy without putting extreme requirements on component stability
c. Good rejection of power supply hum
d. Better resolution compared to all other types of A/D converters for the same number of bits.
Answer:B & C

9. A combinational circuit has three inputs A, B and C and an output F. F is true only for the following combinations.
A is false and B is true
A is false and C is true
A, B and C are all false
A, B and C are all true
a. Write the truth table for F. Use convention, true = 1 and false = 0.
b. Write the simplified expression for F as a sum of products.
c. Write the simplified expression for F as a product of sums.
d. Draw the logic circuit implementation of F using the minimum number of 2 input NAND gates only.


10. Figure shows the memory circuit of 8085 microprocessor.

a. What is the total size of the memory in the circuit?
b. What are the beginning and ending addresses of the memory in chip 1?
c. What are the beginning and ending addresses of the memory in chip 2?
d. Are the memory chips in the circuit ROM or RAM?
e. How will you replace the two NAND gates I the circuit with one 3 to 8 decoder without changing the memory size or the memory addresses? Assume that the decoder has one active high enable E1 and one active low enable E2.


GATE 1993 ECE Video Solutions on Digital Circuits (Digital Electronics)

1. For the logic circuit shown in figure, the output Y is equal to


2. The truth table for the output Y in terms of three inputs A, B and C are given. Draw a logic circuit realization using only NOR gates.

Answer: Y = (A' + B')(B' + C')(A' + C')

3. 2’s complement representation of a 16 bit number (one sign bit and 15 magnitude bits) is FFFF. Its magnitude in decimal representation is
a. 0
b. 1
c. 32,767
d. 65,535

4. Boolean expression for the output of XNOR logic gate with inputs A and B is
a. AB’ + A’B
b. (AB)’ + AB
c. (A’ + B)(A + B’)
d. (A’ + B’)(A + B)

5. A pulse train with a frequency of 1 MHz is counted using a modulo 1024 ripple counter built with JK flip-flops. For proper operation of the counter, the maximum permissible propagation delay per flip flop stage is ____ nsec.
Answer: 50 nSec

6. In a microprocessor, wait states are used to
a. Make the processor wait during a DMA operation
b. Make the processor wait during an interrupt processing
c. Make the processor wait during a power shutdown
d. Interface slow peripherals to the processor

7. Signals A, B, C, D and D’ are available. Using a single 8 to 1 multiplexer and no other gate, implement the Boolean function F(A, B,C, D) = BC + ABD’ + A’C’D


8. A clocked sequential circuit has three states, A, B and C and one input X. As long as the input X is ‘0’, the circuit alternates between the states A and B. if the input X becomes ‘1’(either in state A or in state B), the circuit goes to state C and remains in state C as long as X continues to be 1. The circuit returns to state A if the input becomes ‘0’ once again and from then on repeats its behavior. Assume that the state assignments are A = 00, B = 01 and C = 10.
a. Draw the state diagram of the circuit.
b. Give the state table of the circuit.
c. Draw the circuit using D flip flops.


9. A microprocessor has five address lines [A4 – A0] and eight data lines [D7 – D0]. An input device A, an output device B, a ROM and a RAM are memory mapped to the microprocessor at the addresses as shown in figure. Devices A and B have four addressable registers each/ RAM has 8 bytes and ROM has 16 bytes.

a. Indicate the address lines to be connected to each device and memory.
b. Obtain the minimum sum of product expression for the chip select (CS) function of each device/memory.


Saturday, June 21, 2014

GATE 1994 ECE Video Solutions on Digital Circuits (Digital Electronics)

1. Data can be changed from spatial code to temporal code and vice-versa by using
a. ADCs and DACs
b. Shift registers
c. Synchronous counters
d. Timers

2. The output of a logic gate is ‘1’ when all its inputs are at logic ‘0’. The gate is either
a. a NAND or an EX-OR gate
b. a NOR or an EX-NOR gate
c. an OR r an EX-NOR gate
d. an AND or an EX-OR gate

3. A PLA can be used
a. As a microprocessor
b. As a dynamic memory
c. To realize a sequential logic
d. To realize a combinational logic

4. A dynamic RAM consists of
a. 6 transistors
b. 2 transistors and 2 capacitors
c. 1 transistor and 1 capacitor
d. 2 capacitors only

5. A 2 µsec pulse can be stretched into a 10 msec pulse by using a _______ circuit.
Answer: Monostable Multivibrator

6. Synchronous counters are ________ than the ripple counters.

7. A ring oscillator consisting of 5 inverters is running at a frequency of 1 MHz. the propagation delay per each gate is ________ nsec.
Answer: 100 nSec

8. The carry look ahead adder is a parallel carry adder where all sum digits are generated directly from the input digits. [TRUE / FALSE]
Answer: TRUE

9. In the output stage of a standard TTL, have a diode between the emitter of the pull-up transistor and the collector of the pull-down transistor. The purpose of the diode is to isolate the output node from the power supply VCC. [TRUE / FALSE]
Answer: TRUE

10. Match the following ADC’s with their Maximum conversion time for 8 bit digital output.

Answer: a-2, b-4,c-1

11. A Boolean function, F is given as sum of product (SOP) terms as P = ∑m (3, 4, 5, 6) with A, B and C as inputs. The function, F can be expressed on the karnaugh’s map shown below.

a. Implement this function on an 8:1 MUX
b. What will be the minimized SOP expression for F2.


12. For the digital circuit shown in the figure, explain what happens at nodes N1, N2, F and F’ when


Thursday, June 19, 2014

GATE 1995 ECE Video Solutions on Digital Circuits (Digital Electronics)

1. The output of the circuit shown in figure is equal to


2. The minimum number of NAND gates required to implement the Boolean function A + AB’ + AB’C is equal to
a. Zero
b. 1
c. 4
d. 7

3. A switch-tail ring counter is made by using a single D flip flop. The resulting circuit is a
a. SR flip flop
b. JK flip flop
c. D flip flop
d. T flip flop

4. When a CPU is interrupted, it
a. Stops executing of instructions
b. Acknowledges interrupt and branches of subroutine
c. Acknowledges interrupt and continues
d. Acknowledges interrupt and waits for the next instruction from the interrupt device

5. The minimum number of MOS transistors required to make a dynamic RAM cell is
a. 1
b. 2
c. 3
d. 4

6. An SR latch is a
a. Combinational circuit
b. Synchronous sequential circuit
c. One bit memory element
d. One clock delay element

7. A ‘DMA’ transfer implies
a. Direct transfer of data between memory and accumulator
b. Direct transfer of data between memory and I/O devices without use of µP
c. Transfer of data exclusively within µP registers
d. A fast transfer of data between µP and I/O devices

8. An ‘Assembler’ of a microprocessor is used for
a. Assembly of processors in a production line
b. Creation of new program’s using different modules
c. Translation of a program form assembly language to machine language
d. Translation of a higher level language into English text

9. For a TTL gate, match the following

Answer: a-1, b-4, c-3, d-5

10. For an ADC, match the following

Answer: a-4, b-3, c-2

11. A ROM is used to implement the Boolean functions given below.

a. What is the minimum size of the ROM required?
b. Determine the data in each location of the ROM


12. A hypothetical CPU has a parallel address bus, a parallel data bus, a RD and WR active LOW signals. Two ROMs of size 4K words each and two RAMs of sizes 16K and 8K words, respectively, are to be connected to the CPU. The memories are to be so connected that they fill the address space of the CU as per the memory map shown in the figure. Assuming tat chip select signals are active LOW.

a. What is the number of lines in the address bus of the CPU?
b. Determine the values of address X, Y, Z and W as decimal numbers.
c. Using a 2 to 4 decoder and some additional gates, draw a circuit for the decoding logic.


13. A ‘code converter’ is to be designed to convert from the BCD (5421) code to normal BCD (8421) code. The input BCD combinations for each digit are given below. A block diagram of the converter is shown in figure.
a. Draw K- map for outputs W, X, Y and Z
b. Obtain minimized expression for the outputs W, X, Y and Z


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