4. The initial contents of the 4 bit serial in serial out, right shift, shift register shown in figure, are 0110. After three clock pulses are applied, the contents of the shift register will be
Solution : https://www.youtube.com/watch?v=0VtDZLpnhOM
2. A pulse train can be delayed by a finite number of clock periods using a
a. Serial In Serial Out shift register
b. Serial In Parallel Out shift register
c. Parallel In serial Out shift register
d. Parallel In parallel Out shift register
11. A 4 bit shift register, which shifts 1 bit to the right at every clock pulse, is initialized to values 1000 for (Q0Q1Q2Q3). The D input is derived from Q0, Q2 and Q3 through two XOR gates as shown in figure.
a. Write the 4 bit values (Q0Q1Q2Q3) after each clock pulse till the pattern (1000) reappears on (Q0Q1Q2Q3).
b. To what values should the shift register be initialized so that the pattern (1001) occurs after the first clock pulse?
Solution : https://www.youtube.com/watch?v=w--ZTa4Udk0
15. Circuit shown in the figure is an NMOS shift register. All transistors are NMOS enhancement type with threshold voltage VT = 1 volt. Supply used is VDD = 5 volts.
Two non- overlapping clocks ø1 and ø2 are as shown in the figure is and have large pulse widths.
All capacitors are initially discharged and the Vin = 0 volts is applied. If values of capacitors are C1 = 2 pF and C2 = 1 pF. Find out voltage VC2 on capacitor C2 after ø2 goes low. Neglect body effect on VT in your evaluation.
Solution : https://www.youtube.com/watch?v=fa7OqcOcap0
4. Choose the correct one from among the alternatives A,B,C,D after matching an item from Group 1 with the most appropriate item in Group 2.
P: Shift Register
1: Frequency division
2: Addressing in memory chips
3: Serial to Parallel data conversion
a. P – 3, Q – 2, R – 1
b. P – 3, Q – 1, R – 2
c. P – 2, Q – 1, R – 3
d. P – 1, Q – 2, R – 2
Solution : https://www.youtube.com/watch?v=2d-9lEnp3x8
4. For the circuit shown, two 4-bit parallel in serial out shift registers loaded with the data shown are used to fed the data to a full adder. Initially, all the flip-flops are in clear state. After applying two clock pulses, the outputs sum and carry of the full adder should be ……respectively.
a. 0, 0
b. 0, 1
c. 1, 0
d. 1, 1
Solution : https://www.youtube.com/watch?v=8xaQJ8NM_p4