**1989**

1.
Indicate which of the following
logic gates can be used to realized all possible combinational logic functions
:

a. OR gates only

b. NAND gates only

c. EX-OR gates only

d. NOR gates only

**Answer:**B & D

**Solution :**https://www.youtube.com/watch?v=zOkL4jMirYM

**1990**

1.
The number of Boolean functions that
can be generated by n variables is equal to :

2.
The minimal function that can detect
a “divisible by 3” 8421 BCD code digit (representation is D

_{8}D_{4}D_{2}D_{1}) is given by**Answer:**B

**1992**

1.
A combinational circuit has three
inputs A, B and C and an output F. F is true only for the following
combinations.

A is false and B is true

A is false and C is true

A, B and C are all false

A, B and C are all true

a. Write the truth table for F. Use convention, true = 1 and
false = 0.

b. Write the simplified expression for F as a sum of products.

c. Write the simplified expression for F as a product of sums.

d. Draw the logic circuit implementation of F using the minimum
number of 2 input NAND
gates only.

**1993**

1.
Signals A, B, C, D and D’ are
available. Using a single 8 to 1 multiplexer and no other gate, implement the
Boolean function F(A, B,C, D) = BC + ABD’ + A’C’D

**1994**

1.
The carry look ahead adder is a
parallel carry adder where all sum digits are generated directly from the input
digits. [TRUE / FALSE]

**Answer:**TRUE

2. A Boolean function, F is given as sum of product (SOP) terms
as P = ∑m
(3, 4, 5, 6) with A, B and C as inputs. The function, F can be expressed on the
karnaugh’s map shown below.

a.
Implement this function on an 8:1
MUX

b.
What will be the minimized SOP
expression for F

^{2}.**1995**

1. A ‘code converter’ is to be designed to convert from the BCD
(5421) code to normal BCD (8421) code. The input BCD combinations for each
digit are given below. A block diagram of the converter is shown in figure.

a. Draw K- map for outputs W, X, Y and Z

b. Obtain minimized expression for the outputs W, X, Y and Z

**1997**

1.
A two bit binary multiplier can be implemented
using

a. 2 input AND gates only

b. 2 input XOR gates and 2 input AND gates only

c. Two 2 input NOR gates
and one XOR gate

d. XOR gates and shift registers

**1999**

1.
For a binary half – subtractor
having two inputs A and B, the correct set of logical expressions for the
outputs D (= A minus B) and X (= borrow) are

**Answer:**C

2. In a certain application, four inputs A, B, C, D (both true
and complement forms available) are fed to logic circuit, producing an output F
which operates a relay. The relay turns on when F(ABCD) = 1 for the following
states of the inputs (ABCD): ‘0000’, ‘0010’, ‘0101’, ‘0110’, ‘1101’ and ‘1110’.
States ‘1000’ and ‘1001’ do not occur, and for the remaining states, the relay
is off. Minimize F with the help of a Karnaugh map and realize it using a
minimum number of 3 input NAND gates.

**2000**

1. The operating conditions (ON = 1 and OFF = 0) of three pumps
(x, y, z) are to be monitored, x = 1 implies that pump x is on. It is required
that the indicator (LED) on the panel should glow when a majority of the pumps
fail.

a.
Enter the logical values in the K
map in the format shown in figure. Derive the minimal

Boolean sum of products expression
whose output is zero when a majority of the pumps fail.

b.
The above expression is implemented
using logic gates, and point P is the output of the

circuit, as shown in given figure, P
is at 0 volts when a majority of the pumps fails and is at 5 volts otherwise.
Design a circuit to derive the LED using this output.

The current through the LED should
be 10 mA and the voltage drop across it is 1 volt. Assume that P can source or
sink 10 mA and a 5 volts supply is available.

2. A one bit full adder is to be implemented using 8 to 1
multiplexers (MUX).

a. Write the truth table for sum (S) and carry to the next
stage (C

_{N}), in terms of the two bits (A, B) and the carry from the previous stage (C_{P}). The truth table should be in the ascending order of (A, B, C_{P}) i.e. (000, 001, 010..... etc).
b. Implement S and C

_{N}using 8 to 1 multiplexers.**2001**

1.
For the ring oscillator shown in the
figure, the propagation delay of each inverter is 100 pico sec. What is the
fundamental frequency of the oscillator output?

a. 10 MHz

b. 100 MHz

c. 1 GHz

d. 2 GHz

**Answer:**C

2.
In the figure, the LED

a. Emits light when both S

_{1}and S_{2}are closed.
b. Emits light when both S

_{1}and S_{2}are open.
c. Emits light when only of S

_{1}or S_{2}is closed.
d. Does not emit light, irrespective of the switch positions.

**Answer:**D

_{3},S

_{2},S

_{2},S

_{0}), where S

_{3}is MSB and S

_{0}is LSB. Y is given in terms of minterms as Y = Î£m(1,5,6,7,11,12,13,15) and its complement is given as Î£m(0,2,3,4,8,9,10,14).

a. Enter the logical values in the given Karnaugh map in the
figure, for the output Y.

b. Write down the expression for Y in sum of products form
using minimum number of terms.

c. Draw the circuit for the digital logic boxes using four 2
input NAND gates only for each of the
boxes.

**2002**

1.
If the inputs X

_{3}, X_{2}, X_{1}, X_{0}to the ROM in the figure are 8-4-2-1 BCD numbers, then the outputs Y_{3}Y_{2}Y_{1}Y_{0}are
a. Gary code numbers

b. 2-4-2-1 BCD numbers

c. Excess-3 code numbers

d. None of the above

**Answer:**B

**2003**

1.
The circuit shown in the figure has
4 boxes each described by inputs P,Q,R and outputs Y, Z with the following
relation.

The
circuit acts as a

a. 4 bit adder giving P + Q

b. 4 bit subtractor giving P – Q

c. 4 bit subtractor giving Q – P

d. 4 bit adder giving P + Q + R

2. The circuit shown in the figure converts

a. BCD to Binary code

b. Binary to Excess – 3 code

c. Excess – 3 code to Gray code

d. Gray to Binary code

**2004**

1. A Boolean function f of two variables x and y is defined as
follows:

f(0,0) = f(0,1) = f(1,0) = 1; and
f(1,0) = 0

Assuming complements of x and y are
not available, a minimum cost solution for realizing f using only 2 input NOR
gates and 2 input OR gates (each having unit cost) would have a total cost of

a. 1 unit

b. 4 units

c. 3 unit

d. 2 units

**Answer:**D

3. A digital system is required to amplify a binary encoded
audio signal. The user should be able to control the gain of the amplifier from
a minimum to a maximum in 100 increments. The minimum number of bits required
to encode in straight binary is

a. 8

b. 6

c. 5

d. 7

**Answer:**D

**Solution :**https://www.youtube.com/watch?v=uugIEsYHScg

**2006**

1.
The point P in the following figure
is stuck-at-1. The output f will be

**Answer:**D

**2009**

**Statement for linked answer questions: 1 & 2**

Two products are sold from a vending
machine, which has two push buttons P

_{1}and P_{2}. When a button is pressed, the price of the corresponding product is displayed in a 7-segment display.
If no buttons are pressed, ‘0’ is
displayed, signifying ‘Rs. 0’.

If only P

_{1}is pressed, ‘2’ is displayed, signifying ‘Rs. 2’.
If only P

_{2}is pressed, ‘5’ is displayed, signifying ‘Rs. 5’.
If both P

_{1}and P_{2}are pressed, ‘E’ is displayed, signifying ‘Error’.
The names of the segments in the
7-segment display, and the glow of the display for ‘0’, ‘2’, ‘5’ and ‘E’ are
shown below.

Consider

(i)
Push button pressed / not pressed is
equivalent to logic 1 / 0 respectively

(ii)
A segment glowing / not glowing in
the display is equivalent to logic 1 / 0 respectively

1.
If segments a to g are considered as
functions of P

_{1}and P_{2}, then which of the following is correct?**Answer:**B

2.
What are the minimum numbers of NOT
gates and 2-inout OR gates required to design the logic of the driver for this
7-segment display?

a. 3 NOT and 4 OR

b. 2 NOT and 4 OR

c. 1 NOT and 3 OR

d. 2 NOT and 3 OR

**Answer:**D

**Solution (6 & 7) :**https://www.youtube.com/watch?v=njEr-LoSbw4

**2010**

1.
In the circuit shown, the device
connected to Y5 can have address in the range

a. 2000 – 20FF

b. 2D00 – 2DFF

c. 2E00 – 2EFF

d. FD00 – FDFF

**Answer:**B

**Solution :**https://www.youtube.com/watch?v=5P58M5A7t2U

**2012**

1.
The output Y of a 2-bit comparator
is logic 1 whenever the 2 bit input A is greater than the 2 bit input B. The
number of combinations for which the output is logic 1, is

a.
4

b. 6

c.
8

d. 10

**Answer:**B

**Solution :**https://www.youtube.com/watch?v=W4Sr4YqbM4A

**2013**

1.
A bulb in a staircase has two
switches, one switch being at the ground floor and the other one at the first
floor. The bulb can be turned ON and also can be turned OFF by any one of the
switches irrespective of the state of the other switch. The logic of switching
of the bulb resembles

a. An AND gate

b. An OR gate

c. An XOR gate

d. A NAND gate

**Answer:**C

2.
In the circuit shown below, Q

_{1}has negligible collector to emitter saturation voltage and the diode drops negligible voltage across it under forward bias. If V_{CC}is +5 volts, X and Y are digital signals with 0 volts as logic 0 and V_{CC}as logic 1, then the Boolean expression for Z is**Answer:**B

**Solution :**https://www.youtube.com/watch?v=v85cfm1sDGs

**2014**

1.
For an n – variable Boolean
function, the maximum number of prime implicants is

a. 2(n – 1)

b. n/2

c. 2

^{n}
d. 2

^{(n – 1)}**Answer:**D

2.
In a half-subtractor circuit with X
and Y as inputs, the Borrow (M) and Difference (N = X – Y) are given by

**Answer:**C

3. A 16 bit ripple carry adder is
realized using 16 identical full adders (FA) as shown in the figure. The carry
propagation delay of each FA is 12 ns and the sum propagation delay of each FA
is 15 ns. The worst case delay (in ns) of this 16 – bit adder will be…………

**Answer:**195

**Solution :**https://www.youtube.com/watch?v=jVNqRmlWhaU

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