**1992**

1.
The logic realized by the circuit
shown in figure is

**Answer:**B

**2000**

1. A one bit full adder is to be implemented using 8 to 1
multiplexers (MUX).

a. Write the truth table for sum (S) and carry to the next
stage (C

_{N}), in terms of the two bits (A, B) and the carry from the previous stage (C_{P}). The truth table should be in the ascending order of (A, B, C_{P}) i.e. (000, 001, 010..... etc).
b. Implement S and C

_{N}using 8 to 1 multiplexers.**2001**

1.
In the TTL circuit in the figure, S

_{2}to S_{0}are select lines and X_{7}to X_{0}are input lines. S_{0}and X_{0}are LSBs. The output Y is**Answer:**D

**2002**

1.
The inputs to a digital circuit shown in figure is are
the external signals A, B and C. Assume complements of A, B and C are not
available. The +5 volts power supply (logic 1) and the ground (logic 0) are
also available.

a. Write down the output function in its canonical SOP and POS
forms.

b. Implement the circuit using only 2 to 1 multiplexers shown
in the figure, where S is the data select line, D

_{0}and D_{1}are the input data lines and Y is the output line. The function table is also given for the multiplexer.**2003**

1.
Without any additional circuitry, an
8:1 MUX can be used to obtain

a.
Some but not all Boolean functions
of 3 variables

b.
All functions of 3 variables but
none of 4 variables

c.
All functions of 3 variables and
some but not all of 4 variables

d.
All functions of 4 variables

**2004**

1.
The minimum number of 2 to 1
multiplexers required to realize a 4 to 1 multiplexer is

a.
1

b.
2

c.
3

d.
4

**Answer:**C

**Solution :**https://www.youtube.com/watch?v=vq8UAnVdqzA

**2005**

1.
The Boolean function f implemented
in the figure using two input multiplexers is

**Answer:**A

**Solution :**https://www.youtube.com/watch?v=gWh-fumZFRI

**2007**

1. In the following circuit X is given by

**Answer:**A

**Solution :**https://www.youtube.com/watch?v=pB5R0vNLQR0

**2008**

1.
For the circuit shown in the following
figure, I

_{0}– I_{3}are inputs to the 4:1 multiplexer, R(MSB) and S are control inputs. The output Z can be represented by**Answer:**A

**2009**

1.
What are the minimum number of 2 to
1 multiplexers required to generated a 2 input AND gate and a 2 input EX-OR
gate?

a.
1 and 2

b.
1 and 3

c.
1 and 1

d.
2 and 2

**Answer:**A

**Solution :**https://www.youtube.com/watch?v=wixmXaKDQ5Q

**2010**

1.
The Boolean function realized by the
logic circuit shown is

a.
F = ∑m(0,1,3,5,9,10,14)

b.
F = ∑m(2,3,5,7,8,12,13)

c.
F = ∑m(1,2,4,5,11,14,15)

d.
F = ∑m(2,3,5,7,8,9,12)

**Answer:**D

**Solution :**https://www.youtube.com/watch?v=pOgzYeepujg

**2011**

1.
The logic function implemented by
the circuit below is (ground implies a logic ‘0’)

a.
F = AND (P,Q)

b.
F = OR (P,Q)

c.
F = XNOR (P,Q)

d.
F = XOR (P,Q)

**Answer:**D

**2014**

1.
Consider the multiplexer based logic
circuit shown in the figure.

**Answer:**D

2.
In the circuit shown, W and Y are
MSBs of the control inputs. The output F is given by

**Answer:**C

**Solution :**https://www.youtube.com/watch?v=QUrG-AIkZ4g

3.
If X and Y are inputs and the
Difference (D = X – Y) and the Borrow (B) are the outputs, which one of the
following diagrams implements a half-subtractor?

**Answer:**A

**Solution :**https://www.youtube.com/watch?v=Y2hhJ5DqloE

4.
An 8 – to – 1 multiplexer is used to
implement a logical function Y as shown in the figure. The output Y is given by

**Answer:**C

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