Saturday, November 15, 2014

Previous GATE Questions on Analog to Digital & Digital to Analog Converters (ADCs and DACs) (1987 - Till Date)


1.       Which of the following resistance networks can be used as 3 bit R-2R ladder DAC? Assume Vo corresponds to LSB.

                        a.       Both (i) and (ii)
                        b.      Both (i) and (iii)
                        c.       Only (iii)
                        d.   Only (ii)
Answer:      C
                                   Solution :


1.       Dual slope integration type analog to digital converter provide
            a.       Higher speeds compared to all other types of A/D converters
            b.      Very good accuracy without putting extreme requirements on                              
                   component stability
            c.       Good rejection of power supply hum
            d.      Better resolution compared to all other types of A/D converters for the same number of bits.
Answer:     B & C
Solution :


1.       Data can be changed from spatial code to temporal code and vice-versa by using
                        a.       ADCs and  DACs
                        b.      Shift registers
                        c.       Synchronous counters
                        d.      Timers
Answer:     Shift registers

2.   Match the following ADC’s with their Maximum conversion time for 8 bit digital output.
Answer:     a-2, b-4,c-1


1.   For an ADC, match the following

Answer:     a-4, b-3, c-2


1.       A 12 bit ADC is operating with a 1 µsec clock period and the total conversion time is seen to be 14 µsec. the ADC must be of the
                        a.       Flash type
                        b.      Counting type
                        c.       Integrating type
                        d.      Successive Approximation type
Answer:    D
               Solution : 

2.       A 10 bit ADC with full scale output voltage of 10.24 volts is designed to have a ±LSB/2 accuracy. If the ADC is calibrated at 25oC and the operating temperature ranges from 0oC to 50oC, then the maximum net temperature coefficient of the ADC should not exceed
                        a.       ± 200 µV/oC 
                        b.      ± 400 µV/oC
                        c.       ± 600 µV/oC
                        d.      ± 800 µV/oC
               Solution :      


1.       The advantage of using a dual slope ADC in a digital voltmeter is that
                        a.       Its conversion time is small
                        b.      Its accuracy is high
                        c.       It gives output in BCD format
                        d.      It does not require a comparator
Answer:    B
                 Solution :    

2.   The current I flowing through resistance ‘r’ in the circuit shown is 
a.       -V/12R
b.      V/12R
c.       V/6R
d.      V/3R
Answer:    B
                 Solution :    


1.       The resolution of a 4 bit counting ADC is 0.5 volts. For an analog input of 6.6 volts, the digital output of the ADC will be
                        a.       1011
                        b.      1101
                        c.       1100
                        d.      1110
Answer:    D
                 Solution : 


1.       The number of comparators  in a 4 bit flash ADC is
                        a.       4
                        b.      5
                        c.       15
                        d.      16
Answer:    C
                 Solution :

2.       An 8 bit successive approximation analog to digital converter has full scale reading of 2.55 volts and its conversion time for an anlog input of 1 volt is 20 µs. The conversion time for a 2 volts input is
                        a.       10 µs
                        b.      20 µs
                        c.       40 µs
                        d.      50 µs
Answer:    B
                 Solution :

3.       The most commonly used  amplifier in sample and hold circuits is
                        a.       A unity gain inverting amplifier
                        b.      A unity gain non inverting amplifier
                        c.       An inverting amplifier with a gain of 10
                        d.      An inverting amplifier with a gain of 100
Answer:    B
                 Solution :   

4.       For the 4 bit DAC shown, the output voltage Vo is 
                        a.       10 volts
                        b.      5 volts
                        c.       4 volts
                        d.      8 volts
Answer:    B
                 Solution :


1.       A monochrome video signal that ranges from 0 to 8 volts is digitized using an 8-bit ADC.
            a.       Determine the resolution of the ADC in V/bit.
            b.      Calculate the mean squared quantization error.
            c.       Suppose the ADC is counter controlled. The counter is up counter and positive edge triggered with clock frequency 1 MHz. What is the time taken in     seconds to get a digital equivalent of 1.59 volts?

           Solution :    


1.       The number of comparators required in a 3 bit comparator type ADC is
                        a.       2
                        b.      3
                        c.       7
                        d.      8
Answer:    C
                 Solution :


1.       The minimum number of comparators required to build an 8 bit flash ADC is
                        a.       8
                        b.      63
                        c.       255
                        d.      256
Answer:    C
                 Solution :

2.   The circuit shown in the figure is a 4 bit DAC.
      The input bits 0 and 1 are represented by 0 volts and 5 volts respectively. The OP-AMP is ideal, but all the resistances and the 5 volts inputs have a tolerance o f ± 10%. The specification (rounded to the nearest multiple of 5%) for the tolerance of the DAC is
                        a.       ± 35%
                        b.      ± 20%
                        c.       ± 10%
                        d.      ± 5%

Answer:     A
                   Solution :


1.       A 4 – bit D/A converter is connected to a free running 3 – bit UP counter, as shown in the following figure. Which of the following waveforms will be observed at Vo?

Answer:    B
                Solution :


Statement for linked answer questions 1 & 2:
In the Digital to analog converter circuit shown in the figure below, VR = 10 volts and R = 10 k

1.   The current i is
                        a.       31.25 µA 
                        b.      62.5 µA
                        c.       125 µA
                        d.      250 µA
Answer:  B  
2.   The voltage Vo is
                        a.       – 0.781 volts 
                        b.      – 1.562 volts
                        c.       – 3.125 volts
                        d.      – 6.250 volts
Answer:    C
               Solution (1 & 2) :


Statement for Linked Answer Questions 1 and 2:
            In the following circuit, the comparator output is logic ‘1’ if V+ > V- and is logic ‘0’  
                 otherwise. The D/A conversion is done as per the relation.
                 The counter starts from the clear state.

1.       The stable reading of the LED display is
                        a.       06
                        b.      07
                        c.       12
                        d.      13
Answer:    D
2.       The magnitude of the error  between VDAC and Vin at steady state in volts is
                        a.       0.2
                        b.      0.3
                        c.       0.5
                        d.      1.0
Answer:    B
               Solution (1 & 2) :


1.       The output of a 3 stage Johnson (twisted ring) counter is fed to a digital to analog (D/A) converter as shown in the figure below. Assume all states of the counter to be unset initially. The waveform which represents the D/A converter output Vo is

Answer:    A
                Solution :


1.       An analog voltage in the range 0 to 8 volts is divided in 16 equal intervals for conversion to 4 – bit digital output. The maximum quantization error (in volts) is ………..
Answer:    0.25
                 Solution :

2.       For a given sample and hold circuit, if the value of the hold capacitor is increased, then
            a.       Droop rate decreases and Acquisition time decreases 
            b.      Droop rate decreases and Acquisition time increases
            c.       Droop rate increases and Acquisition time decreases
            d.      Droop rate increases and Acquisition time increases
Answer:    B
                 Solution :

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