Tuesday, October 28, 2014

GATE Questions on Junction Field Effect Transistor (JFET) - 1987 to Till Date

6.       The pinch off voltage for an n-channel JFET is 4 volts, then pinch off occurs for VDS when VGS = -1 volts is
                        a.       3 volts
                        b.      5 volts
                        c.       4 volts
                        d.      1 volts
Answer:    A
              Solution : https://www.youtube.com/watch?v=6dIMNQ-GqKM

3.       In an N-channel JFET, VGS is held constant. VDS is less than the breakdown voltage. As VDS is increased…(Assume ‘S’ as conducting cross sectional area of the channel and ‘J’ as channel current density)
                        a.       ‘S’ increases and ‘J’ increases 
                        b.      ‘S’ decreases and ‘J’ decreases
                        c.       ‘S’ decreases and ‘J’ increases
                        d.      ‘S’ increases and ‘J’ decreases
Answer:   C
                 Solution : https://www.youtube.com/watch?v=5wE7t_1k180


6. The pinch off voltage of a JFET is 5.0 volts. Its cutoff voltage is

Answer:    5 VOLTS
                 Solution :  https://www.youtube.com/watch?v=YZcn5Y_9p14

7.  Which of the following effects can be caused by a rise in the temperature ?
       a. Increase in MOSFET current
       b. Increase in BJT current
       c. Decrease in MOSFET current
       d. Decrease in BJT current

Answer:    B & C
                 Solution : https://www.youtube.com/watch?v=BoRoLQ2eN6o


   6.       The built in potential of the gate junction of an n-channel JFET is 0.5 volts. The drain current saturated at VDS = 5 volts when VGS = 0 volts. The pinch off voltage is …………..
Answer:  4 VOLTS

    11.        It is required to use a JFET of figure as linear resistor. The parameters of the JFET are as follows. W = 100 µm, L = 10 µm and a = 2.5 µm.  The doping in the n-layer is ND = 1016 cm-3 and the electron mobility is 1500 cm2/V-sec. the depletion layer width of each junction due to the built in potential is 0.25 µm. The two P+ gate regions are connected together externally. The resistances of the regions outside the gate are negligible. Determine the minimum value of the linear resistor which can be realized using this JFET without forward biasing the gate junctions.      

Answer:      RDSmin = 208.33 Ω   
Solution :  https://www.youtube.com/watch?v=wF6PSs84WuM


5.       An n-channel JFET has a pinch off voltage VP = -5 volts, VDSmax = 20 volts, and gm = 2 mA/V. The minimum ON resistance is achieved in the JFET for …………

a.       VGS = - 7 volts  and  VDS = 0 volts
b.      VGS =   7 volts  and  VDS = 0 volts
c.       VGS =   0 volts  and  VDS =  20 volts
d.      VGS = - 7 volts  and  VDS =  20 volts

Answer:   B

                 Solution :  https://www.youtube.com/watch?v=cYU2g2VQi18

6.       The JFET in the circuit shown has an IDSS = 10 mA and VP = 5 volts. The value of the resistance RS for a drain current IDS of 6.4 mA is …………….. (Select the nearest value).

Answer:   A

                 Solution :   https://www.youtube.com/watch?v=-NaCMt2yT8w

4.       The transit time of the current carriers through the channel of an FET decides its ……………. characteristics.
Answer:   Switchimg
                 Solution : https://www.youtube.com/watch?v=vQJjmHNsn3I

12.   An n-channel JFET has IDSS = 1 mA and VP = -5 volts. Its maximum Transconductance is ……..
Answer:    0.4 mS
               Solution :   https://www.youtube.com/watch?v=mXxiWhP59fQ

14.   In a JFET, if

Answer:    a-3, b-3, c-4
               Solution :   https://www.youtube.com/watch?v=Ll4flWTSUbY


2.       A JFET with VP = -4 volts and IDSS = 12 mA is used in the circuit shown. Assuming the device to be operating in saturation.

        a.       Determine ID, VDS and VGS.

        b.      Check to confirm that the device is indeed operating in saturation.

Answer:    4 mA, 4 volts, -4 volts
                  Solution :   https://www.youtube.com/watch?v=LLaKuQZnC00


4.       Two identical FETs, each characterized by the parameters gm and rd are connected in parallel. The composite FET is then characterized by the parameters

a.       gm/2  and  2rd 
b.      gm/2  and   rd/2
c.       2gm    and   rd/2
d.      2gm    and   2rd 

Answer:   C
               Solution :  https://www.youtube.com/watch?v=uXLjYKEeZIQ

7..       The JFET in the circuit of figure is characterized by the parameters IDSS = 4 mA and Vp = -4 volts.               
                            Find            (a) Vo   if   Vi = 0     and      (b) Vi   if   Vo = 0

Answer:    (a) Vo = - VGS when Vi = 0 volts, and (b) Vi = 0.5 volts when Vo = 0 volts
                Solution :  https://www.youtube.com/watch?v=_5yCMN_4xO0


   3.       An n-channel JFET has IDSS = 2 mA and Vp = -4 volts. Its Transconductance gm in mS for an  

         applied gate to source voltage of -2 volts is 
                        a.       0.25
                        b.      0.50
                        c.       0.75
                        d.      1.0
Answer:   B

13.   The action of a JFET in its equivalent circuit can best be represented as a
                        a.       Current controlled current source
                        b.      Current controlled voltage source
                        c.       Voltage controlled current source
                        d.      Voltage controlled voltage source
Answer:  C
                Solutoin :  https://www.youtube.com/watch?v=gF67tPBH9M8

7.       Group I lists four different semiconductor devices. Match each device in Group I with its characteristic property in Group II.
Answer:   C


10.   The cross section of a JFET is shown in the figure. Let VG be -2 volts and VP be the initial pinch off voltage. If the width W is doubled (with other geometric parameters and doping levels remaining the same), then the ratio between the mutual Transconductance of the initial and the modified JFET is

Answer:   B
                Solution : https://www.youtube.com/watch?v=i1HcEXiUqXA

7.       Common Data Question:

The channel resistance of an N channel JFET is shown below is 600 Ω, when the full channel thickness (tOX) of 10 µm is available for conduction. The built in voltage of the gate P+N junction is (Vbi) is -1 volts. When the gate to source voltage (VGS) is 0 volts, the channel is depleted by 1 µm on each side due to the built in voltage and hence the thickness available for conduction is only 8 µm. 

i.                     The channel resistance when VGS = 0 volts is
                        a.       480 Ω
                        b.      600 Ω
                        c.       750 Ω
                        d.      1000 Ω
Answer:   C
ii.                   The channel resistance when VGS = -3 volt is
                        a.       360 Ω
                        b.      917 Ω
                        c.       1000 Ω
                        d.      3000 Ω
Answer:   C
               Solution : https://www.youtube.com/watch?v=-Nk0OFZhM-g


Post Your Feedback (or) Doubts here.......


Email *

Message *