Saturday, June 21, 2014

GATE 1994 ECE Video Solutions on Digital Circuits (Digital Electronics)

1. Data can be changed from spatial code to temporal code and vice-versa by using
a. ADCs and DACs
b. Shift registers
c. Synchronous counters
d. Timers

2. The output of a logic gate is ‘1’ when all its inputs are at logic ‘0’. The gate is either
a. a NAND or an EX-OR gate
b. a NOR or an EX-NOR gate
c. an OR r an EX-NOR gate
d. an AND or an EX-OR gate

3. A PLA can be used
a. As a microprocessor
b. As a dynamic memory
c. To realize a sequential logic
d. To realize a combinational logic

4. A dynamic RAM consists of
a. 6 transistors
b. 2 transistors and 2 capacitors
c. 1 transistor and 1 capacitor
d. 2 capacitors only

5. A 2 ┬Ásec pulse can be stretched into a 10 msec pulse by using a _______ circuit.
Answer: Monostable Multivibrator

6. Synchronous counters are ________ than the ripple counters.

7. A ring oscillator consisting of 5 inverters is running at a frequency of 1 MHz. the propagation delay per each gate is ________ nsec.
Answer: 100 nSec

8. The carry look ahead adder is a parallel carry adder where all sum digits are generated directly from the input digits. [TRUE / FALSE]
Answer: TRUE

9. In the output stage of a standard TTL, have a diode between the emitter of the pull-up transistor and the collector of the pull-down transistor. The purpose of the diode is to isolate the output node from the power supply VCC. [TRUE / FALSE]
Answer: TRUE

10. Match the following ADC’s with their Maximum conversion time for 8 bit digital output.

Answer: a-2, b-4,c-1

11. A Boolean function, F is given as sum of product (SOP) terms as P = ∑m (3, 4, 5, 6) with A, B and C as inputs. The function, F can be expressed on the karnaugh’s map shown below.

a. Implement this function on an 8:1 MUX
b. What will be the minimized SOP expression for F2.


12. For the digital circuit shown in the figure, explain what happens at nodes N1, N2, F and F’ when


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