### GATE 2003 ECE Video Solution on Digital Circuits (Digital Electronics)

1. The number of distinct Boolean expressions of 4 variables is
a. 16
b. 256
c. 1024
d. 65536

2. The minimum number of comparators required to build an 8 bit flash ADC is
a. 8
b. 63
c. 255
d. 256

3. The output of the 74 series of TTL gates is taken from a BJT in
a. Totem pole and Common Collector configuration
b. Either Totem pole or Open Collector configuration
c. Common Base configuration
d. Common Collector configuration

4. Without any additional circuitry, an 8:1 MUX can be used to obtain
a. Some but not all Boolean functions of 3 variables
b. All functions of 3 variables but none of 4 variables
c. All functions of 3 variables and some but not all of 4 variables
d. All functions of 4 variables

5. A 0 to 6 counter consists of 3 flip flops and a combination circuit of 2 input gate(s). The combination circuit consists of
a. one AND gate
b. one OR gate
c. one AND gate and one OR gate
d. two AND gates

6. The circuit shown in the figure has 4 boxes each described by inputs P,Q,R and outputs Y, Z with the following relation. The circuit acts as a
a. 4 bit adder giving P + Q
b. 4 bit subtractor giving P – Q
c. 4 bit subtractor giving Q – P
d. 4 bit adder giving P + Q + R

7. If the functions W, X, Y and Z are as given below, 8. A 4 bit ripple counter and a 4 bit synchronous counter are made using flip flops having a propagation delay of 10 ns each. If the worst case delay in the ripple counter and the synchronous counter be R and S respectively, then
a. R = 10 ns, S = 40 ns
b. R = 40 ns, S = 10 ns
c. R = 10 ns, S = 30 ns
d. R = 30 ns, S = 10 ns

9. The DTL, TTL, ECL and CMOS families of digital ICs are compared in the following 4 columns.
 P Q R S Fanout is minimum DTL DTL TTL CMOS Power consumption is minimum TTL CMOS ECL DTL Propagation delay is minimum CMOS ECL TTL TTL

The correct column is
a. P
b. Q
c. R
d. S

10. The circuit shown in the figure is a 4 bit DAC. The input bits 0 and 1 are represented by 0 volts and 5 volts respectively. The OP-AMP is ideal, but all the resistances and the 5 volts inputs have a tolerance o f ± 10%. The specification (rounded to the nearest multiple of 5%) for the tolerance of the DAC is
a. ± 35%
b. ± 20%
c. ± 10%
d. ± 5%

11. The circuit shown in the figure converts a. BCD to Binary code
b. Binary to Excess – 3 code
c. Excess – 3 code to Gray code
d. Gray to Binary code

12. In the circuit shown in the figure, ‘A’ is a parallel in, parallel out 4 bit shift register, which loads at the rising edge of the clock C. The input lines are connected to a 4 bit bus, W. Its output acts as the input to a 16 X 4 ROM, whose output is floating when the enable input E is 0. A partial table of the contents of the ROM is as follows.
 Address 0 2 4 6 8 10 11 14 Data 0011 1111 0100 1010 1011 1000 0010 1000
The clock to the register is shown, and the data on the W bus at time t1 is 0110. The data on the bus at time t2 is
a. 1111
b. 1011
c. 1000
d. 0010

13. In an 8085 microprocessor, the instruction CMP B has been executed while the content of the accumulator is less than that of register B. As a result,
a. Carry flag will be set but Zero flag will be reset
b. Carry flag will be reset but Zero flag will be set
c. Both Carry flag and Zero flag will be reset
d. Both Carry flag and Zero flag will be set

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