1. For a MOS capacitor fabricated on a P-type semiconductor, strong inversion occurs when

a. Surface potential is equal to Fermi level

b. Surface potential is zero

c. Surface potential is negative is negative and equal to Fermi potential in magnitude

d. Surface potential is positive and equal to twice the Fermi potential

2. In a common emitter BJT amplifier, the maximum usable supply voltage is limited by

a. Avalanche breakdown of base emitter junction

b. Collector base breakdown voltage with emitter open (BV

c. Collector emitter breakdown voltage with base open (BV

d. Zener breakdown voltage of the emitter base junction

3. In the circuit shown, the current flowing through the ideal diode equal to

a. 0 Amp

b. 4 Amp

c. 1 Amp

d. None of the above

4. The intrinsic carrier density at 300

a. n = 1.5 x 10

b. n = 1.5 x 10

c. n = 2.25 x 10

d. n = 1.5 x 10

5. The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because

a. The driver transistor has larger threshold voltage than the load transistor

b. The driver transistor has larger leakage currents compared to the load transistor

c. The load transistor has a smaller W/L ratio compared to the driver transistor

d. None of the above

6. In the cascade amplifier circuit shown, determine the values of R

7. Given NMOS circuit as shown. The specifications of the circuit are :

V

Evaluate V

8. Find static noise margins for a BJT inverter shown in figure. Transistor used is an NPN type with the specifications as follows.

9. For a typical NPN transistor, the following data are available :

W

W

Base doping = 5 X 10

Minority carrier life time in the base region is τ

10. An n-type silicon bar is doped uniformly by phosphorous atoms to a concentration 4.5 X 10

Assume optical generation rate as 10

Evaluate the hole and electron diffusion currents at x = 36.4 µm.

Answer:

a. Surface potential is equal to Fermi level

b. Surface potential is zero

c. Surface potential is negative is negative and equal to Fermi potential in magnitude

d. Surface potential is positive and equal to twice the Fermi potential

**Solution :**https://www.youtube.com/watch?v=351K-p6NM-k

2. In a common emitter BJT amplifier, the maximum usable supply voltage is limited by

a. Avalanche breakdown of base emitter junction

b. Collector base breakdown voltage with emitter open (BV

_{CBO})c. Collector emitter breakdown voltage with base open (BV

_{CEO})d. Zener breakdown voltage of the emitter base junction

**Solution :**https://www.youtube.com/watch?v=MvgbR_ljMtk

3. In the circuit shown, the current flowing through the ideal diode equal to

a. 0 Amp

b. 4 Amp

c. 1 Amp

d. None of the above

**Solution :**https://www.youtube.com/watch?v=lsgn8Hnz6HE

4. The intrinsic carrier density at 300

^{o}K is 1.5 X 10^{10}per cm^{3}for silicon. For n-type silicon doped to 2.25 X 10^{15}atoms/cm^{3}, the equilibrium electron and hole densities area. n = 1.5 x 10

^{15}/cm^{3}, p = 1.5 x 10^{10}/cm^{3}b. n = 1.5 x 10

^{10}/cm^{3}, p = 2.25 x 10^{15}/cm^{3}c. n = 2.25 x 10

^{15}/cm^{3}, p = 1.5 x 10^{5}/cm^{3}d. n = 1.5 x 10

^{10}/cm^{3}, p = 1.5 x 10^{10}/cm^{3}**Solution :**https://www.youtube.com/watch?v=PCnFSBDZldQ

5. The gate delay of an NMOS inverter is dominated by charge time rather than discharge time because

a. The driver transistor has larger threshold voltage than the load transistor

b. The driver transistor has larger leakage currents compared to the load transistor

c. The load transistor has a smaller W/L ratio compared to the driver transistor

d. None of the above

**Solution :**https://www.youtube.com/watch?v=D2kfxsy-ypk

6. In the cascade amplifier circuit shown, determine the values of R

_{1}, R_{2}and R_{L}such that the quiescent current through the transistors is 1 mA and the collector voltages are V_{C1}= 3 volts, and V_{C2}= 6 volts. Take V_{BE}= 0.7 volts and assume β of the transistors is very high and base currents to be negligible.**Solution :**https://www.youtube.com/watch?v=rAgjdD4Zhrg

7. Given NMOS circuit as shown. The specifications of the circuit are :

V

_{DD}= 10 volts, β = µ_{n}C_{ox}(W/L) = 10^{-4}Amp/V^{2}, V_{T}= 1 volt and I_{DS}= 0.5 mA.Evaluate V

_{DS}and R_{D}. Neglect body effect.**Solution :**https://www.youtube.com/watch?v=Uc3EuOto9Pk

8. Find static noise margins for a BJT inverter shown in figure. Transistor used is an NPN type with the specifications as follows.

**Solution :**https://www.youtube.com/watch?v=sKKZZGk1MKc

9. For a typical NPN transistor, the following data are available :

W

_{C}= 20 µm and collector doping = 5 X 10^{18}cm^{-3}W

_{E}= 1 µm and emitter doping = 10 X 10^{19}cm^{-3}Base doping = 5 X 10

^{15}cm^{-3}Minority carrier life time in the base region is τ

_{n}= 5 µsec.**Solution :**https://www.youtube.com/watch?v=e32CFF9BjUk

10. An n-type silicon bar is doped uniformly by phosphorous atoms to a concentration 4.5 X 10

^{13}cm^{-3}. The bar has cross section of 1 mm^{2}and length of 10 cm. It is illuminated uniformly for region x < 0 as shown.Assume optical generation rate as 10

^{21}electron-hole pairs per cm^{3}per second, the hole lifetime and electron lifetime are equal to 1 µsec.Evaluate the hole and electron diffusion currents at x = 36.4 µm.

Answer:

**Solution :**